VIP Video Converter manuels

Manuels d'utilisation et guides de l'utilisateur pour Logiciel VIP Video Converter.
Nous fournissons des manuels en pdf 2 VIP Video Converter à télécharger gratuitement par type de document : Guide de l'utilisateur, Manuel d'utilisateur

Vip Video Converter Guide de l'utilisateur (290 pages)

marque: Vip | Catégorie: Logiciel | Taille: 7.85 MB |

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Table des matières

User Guide

1

Contents

3

Contents v

5

Contents vii

7

Contents ix

9

Additional Information

10

Release Information

12

Device Family Support

12

Features

13

Design Example

14

2D FIR Filter

15

2D Median Filter

15

Alpha Blending Mixer

16

Avalon-ST Video Monitor

17

Chroma Resampler

17

Clocked Video Input

18

Clocked Video Output

19

Color Plane Sequencer

19

Color Space Converter

20

Control Synchronizer

21

Deinterlacer

21

Deinterlacer II

22

Frame Buffer

22

Gamma Corrector

23

Interlacer

23

Notes to Table 1–19:

24

Notes to Table 1–20:

24

Scaler II

25

Test Pattern Generator

26

Trace System

26

Installation and Licensing

27

Design Flows

28

Generated Files

30

Note to Table 2–1:

31

3. Interfaces

33

Avalon-ST Video Protocol

34

Video Data Packets

35

Color Pattern

36

Plane for even rows

37

Plane for odd rows

37

3–6 Chapter 3: Interfaces

38

Control Data Packets

39

3–8 Chapter 3: Interfaces

40

Use of Control Data Packets

41

Ancillary Data Packets

42

Packet Propagation

43

Packet Transfer Examples

44

Parameter Value

45

3–14 Chapter 3: Interfaces

46

Bits per Color Sample 8

47

3–16 Chapter 3: Interfaces

48

Avalon-MM Slave Interfaces

49

3–18 Chapter 3: Interfaces

50

Notes to Table 3–10:

51

Avalon-MM Master Interfaces

52

Chapter 3: Interfaces 3–21

53

3–22 Chapter 3: Interfaces

54

Notes to Table 4–4:

59

Alpha Blending

66

Packet Visualization

74

MegaCore function

76

4:4:4 to 4:2:2

80

4:2:2 to 4:4:4

80

Vertical Resampling (4:2:0)

81

Note to Table 8–3:

84

9. Clipper MegaCore Function

85

Notes to Table 9–3:

87

3FF XYZ00

89

TRS (10bit)

89

D0 D1vid_data

90

Video Locked Signal

91

Format Detection

92

Overflow

95

Control Register Maps

100

Function

103

Functional Description

104

Control Port

106

Video Modes

106

Active lines

107

V blanking

107

V blanking F0 V blank

109

Interrupts

111

Underflow

113

Timing Constraints

114

Error Recovery

115

Parameter Settings

116

Note to Table 11–6:

117

Note to Table 11–7:

119

Note to Table 11–8:

121

Combining Color Patterns

124

Splitting/Duplicating

124

Subsampled Data

125

Notes to Table 12–3:

128

Constant Precision

131

Calculation Precision

131

Operands Page

134

Notes to Table 13–4:

135

Core Overview

145

Deinterlacing Methods

146

Motion-Adaptive

147

Frame Buffering

149

Frame Rate Conversion

150

Notes to Table 15–3:

156

slave address space

157

Note to Table 15–6:

160

Control Map Registers

169

Locked Frame Rate Conversion

178

Interlaced Video Streams

179

Notes to Table 18–3:

182

Note to Table 18–5:

185

Avalon-MM slave interface

189

Note to Table 20–4:

196

21. Scaler MegaCore Function

199

Resource Usage

200

Algorithmic Description

200

Recommended Parameters

206

Note to Table 21–5:

210

Note to Table 21–7:

212

Notes to Table 21–8:

214

January 2013 User Guide

219

23. Switch MegaCore Function

225

Control Register Map

229

[get_service_paths design]

240

TCL Shell Commands

242

Note to Figure A–1:

245

Avalon-ST Video Class Library

246

Figure A–2

248

Requirement

252

Figure A–4. QSys Dialog Box

253

Figure A–5. tb.v Netlist

253

Video File Reader Test

255

Video Field Life Cycle

260

Constrained Random Test

262

Example A–6. Scoreboard

265

Complete Class Reference

267

CHANNELS_PER_PIXEL = 3);

269

Note to Table A–12:

275

Raw Video Data Format

278

Y410 / A2R10G10B10

280

MegaCore Function—In Depth

283

How to Contact Altera

288

Typographic Conventions

288

Additional Information Info–3

289

Info–4 Additional Information

290

Vip Video Converter Manuel d'utilisateur (143 pages)

marque: Vip | Catégorie: Logiciel | Taille: 5.09 MB |

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Table des matières

Altera Video System

1

Memory Bandwidth

2

Altera Video Framework

4

Available Now!

5

Video Development Kits

6

Traditional System Design

7

Qsys automatically

8

Example Design in Qsys

9

ARM AMBA™ AXI™ 3.0

10

Avalon Streaming (ST) Video

11

Standard Interface Example

12

Qsys Interconnect

12

Add IP blocks to the system

13

Start a New System in Qsys

15

Add the VIP Components

16

Add Custom Components

18

Connect the Components

19

Quartus II

22

Eclipse

22

Development

22

Exercise #0

24

Test Pattern Generator

25

Clocked Video Output

25

Video Trace Monitor

25

Clock Video Output

28

No conversion is done to the

28

Debug pipe agnostic

30

Monitor

31

Trace Table View

32

• Video data

33

Up to first 6 beats of

33

Exercise #1

34

Interface Types

35

Structure of packet

36

Video Data Packet

37

Color Pattern

38

Recommended Color Patterns

39

Component

40

Description Bits

40

Parameters

41

Verification

42

What is it?

43

Environment

44

Three types of classes

45

Easy to use :

46

Easy to constrain :

46

Source & sink

47

 Flow :

48

Exercise #2

49

 Part 1:

50

 Part 2:

50

Run-Time Control

51

… … …

52

To update control registers:

53

Software API

54

Nios II

55

Clipper

55

Detects input format

55

Example – Main program

56

Using an embedded processor

57

Processor

58

Master port

58

Video function 1

58

Avalon MM control plane

58

Exercise #3

60

 (Custom) Terminator Block

62

Clock Video Input

63

(such as BT656 and DVI) to

63

Configuration

65

Bypassing An IP Core

66

Avoiding Deadlock

67

Clock locking

68

Frame locking

68

 Poor jitter performance

69

Underflow

71

Overflow

71

 Interlaced @ 29.97 fps

72

 Progressive @ 59.94 fps

72

 74.176 MHz pixel clock

72

Locking procedure

73

Exercise #4

74

Frame Rate Conversion

75

Frame Buffer

76

Triple Buffer Mode

79

• 2x Frame Buffer

81

Deinterlacer (MA)

82

Sample Packing

84

2 accesses at output rate

85

2 x 2.654 = 5.308

85

Use SD for 2

86

channel input

86

Deinterlacer

87

System Interconnect Fabric

87

(UDX Reference Design)

88

Inter-bank data reordering

89

Flexible system interface

89

Multi-cast writes

89

Exercise #5

90

Deinterlacer II

93

The problem - I

94

The problem - II

95

Preferred when

96

Telecine

97

‘Motion bleed’ reduces

98

Total: 10.574Gbit/s

100

The problem - III

101

Maths to the rescue!

102

Incorrect edge direction

103

Correct edge direction

103

Dil II UDX 4 (ACDS 11.1)

104

Dil II UDX 5 (ACDS 12.1)

104

Finally - ACDS 12.1 Release

106

Lower cost (FPGA resources)

107

VIP Function Details

108

Scaler Polyphase Algorithm

108

Resource usage of a N

109

taps scaling engine

109

Recommended parameters

109

Interpolation is not perfect

110

VIP Suite – Scaler II

111

Scaler II – Edge Adaptive

112

Upscale (1)

114

Upscale (2)

115

Downscale (1)

116

Downscale (2)

117

Exercise #6

119

Select the number of

121

Select the size of the image

121

Control Synchronizer

122

Avalon MM

123

Chroma Resampler

124

Exercise #7

125

UDX5 in S4GX

127

UDX 5.1.3 (available now)

128

Edge Adaptive Scaling

128

4K Upscale 3

129

4K Upscale 3 Block Diagram

130

Runs on SIVGX dev kit

131

Available now

131

5 Mega Digital Camera

132

How to Equip with VEEK

133

 Composite video input

134

Key Video Functions

134

 Deinterlacer, Scaler

134

Space Converter, Clipper

134

Input Processing Output

135

 Camera video input

135

 Scaler, Alpha blending

135

 2 video inputs

136

 Composite, Camera

136

 Key Video Functions

136

Demo # 4 – Multi-view

137

Summary

138

View design examples

139

FAE support: 031-776-9888

140

Terasic support

140

Training

141

Thank You!

143

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